A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)
Answer
260.2 to 261.2
Explanation
The clock must fit the slowest stage plus a latch: \(T = 250 + 10 = 260\) ns.
With no stalls, the first instruction takes 5 cycles to pass through the pipeline and each of the other 999 instructions finishes one cycle after the previous one:
\[(5 + 1000 - 1) \times 260 = 1004 \times 260 = 261040\ \text{ns} = 261.04\ \mu\text{s}\]
Using the average stage delay, or leaving out the latch delay, gives a clock that is too short: every stage advances in lockstep, so the slowest stage sets the pace.
Answer: 261.04