GATE CS Pipelining Previous Year Questions

GATE CS 2025 Set 2 | Question 56

NAT · 2 marks

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)

Your answer

Explanation

Answer: 260.2 to 261.2

The clock must fit the slowest stage plus a latch: \(T = 250 + 10 = 260\) ns.

With no stalls, the first instruction takes 5 cycles to pass through the pipeline and each of the other 999 instructions finishes one cycle after the previous one:

\[(5 + 1000 - 1) \times 260 = 1004 \times 260 = 261040\ \text{ns} = 261.04\ \mu\text{s}\]

Using the average stage delay, or leaving out the latch delay, gives a clock that is too short: every stage advances in lockstep, so the slowest stage sets the pace.

Answer: 261.04

GATE CS 2024 Set 1 | Question 30

MSQ · 1 mark

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction Forwarding cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Explanation

Answer: (A), (B), (C)

A: true. This is what forwarding (bypassing) means: a result goes straight from the stage that produces it in an earlier instruction to the stage that needs it in a later one, without waiting for the register write in WB.
B: true. The MEM/WB pipeline register holds what leaves the MEM stage, such as a loaded word, and a forwarding path takes it to the ALU inputs in EX. A loaded value reaches the very next instruction this way after one stall cycle.
C: true. That stall is unavoidable: a loaded value appears only at the end of MEM, while the next instruction needs it at the start of EX in the same cycle.
D: false. Forwarding needs extra paths, multiplexers at the ALU inputs and a forwarding unit that compares register numbers.

Answer: A, B, C

GATE CS 2024 Set 2 | Question 31

MSQ · 1 mark

An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

There is a RAW dependency on R3 between I1 and I2 There is a WAR dependency on R3 between I1 and I3 There is a RAW dependency on R3 between I2 and I3 There is a WAW dependency on R3 between I3 and I4

Explanation

Answer: (A)

Take an earlier instruction and a later one. RAW (read after write) means the later one reads a register that the earlier one writes, WAR means the later one writes a register that the earlier one reads, and WAW means both write the same register. Here R3 is written by I1 and I3 and read by I2 and I4.

A: I1 writes R3 and I2 reads it. RAW, so true.
B: I1 and I3 both write R3, and I1 does not read it. That is WAW, not WAR.
C: I2 reads R3 and the later I3 writes it. That is WAR, not RAW (the RAW between them is on R5).
D: I3 writes R3 and I4 reads it. That is RAW, not WAW; I4 writes R7.

Answer: A

GATE CS 2024 Set 2 | Question 58

NAT · 2 marks

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

Your answer

Explanation

Answer: 2.9 to 3.1

Both designs run at the same 2 GHz clock, so the speedup is the ratio of their cycles per instruction (CPI).

Non-pipelined CPI: 6.
Pipelined CPI: the ideal 1 plus the average stall cycles, \(1 + 0.2 \times 2 + 0.2 \times 3 = 1 + 0.4 + 0.6 = 2\).

Speedup \(= 6 / 2 = 3.0\). The number of stages does not enter the calculation, because the pipelined throughput (1 instruction per cycle) and the non-pipelined cycle count (6) are both given directly.

Answer: 3.0