GATE CS Computer Organization and Architecture Previous Year Questions

GATE CS 2025 Set 1 | Question 11

MCQ · 1 mark · −0.33

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

(iii), (i), (ii) (i), (iii), (ii) (i), (ii), (iii) (iii), (ii), (i)

Explanation

Answer: (A)

A non-pipelined processor checks for interrupts only between instructions, so it first completes the instruction it is executing (iii). Next it saves the program counter (i), which now holds the address of the next instruction, so the interrupted program can continue from there once the ISR returns. Only then is the program counter loaded with the ISR's start address (ii); doing (ii) before (i) would destroy the return address.

Answer: A

GATE CS 2025 Set 1 | Question 27

MSQ · 1 mark

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Data path: Mux_A selects RA or a 32-bit immediate value, Mux_B selects RB or a 32-bit immediate value; both mux outputs feed the ALU, whose result goes to RZ

The data path can implement arithmetic operations involving two registers. The data path can implement arithmetic operations involving one register and one immediate value. The data path can implement arithmetic operations involving two immediate values. The data path can only implement arithmetic operations involving one register and one immediate value.

Explanation

Answer: (A), (B), (C)

Each ALU input comes from its own multiplexer: Mux_A passes either RA or a 32-bit immediate value, and Mux_B passes either RB or a 32-bit immediate value. So every combination of the two operand sources is possible.

(A) True: select RA on Mux_A and RB on Mux_B.
(B) True: select RA and the immediate on Mux_B (or the immediate on Mux_A and RB).
(C) True: select the immediate input on both multiplexers.
(D) False: the word “only” is wrong, because (A) and (C) are also possible.

Answer: A, B, C

GATE CS 2025 Set 1 | Question 36

MCQ · 2 marks · −0.66

Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K=\(2^{10}\), 1M=\(2^{20}\).]

\(6 \times 2^{10}\) \(8 \times 2^{10}\) \(2^{12}\) \(2^{14}\)

Explanation

Answer: (A)

Split the 20-bit address into tag, line index and block offset.

Offset: a block has \(16 = 2^4\) bytes, so 4 bits.
Index: the cache has \(2^{14} / 2^4 = 2^{10}\) lines, so 10 bits.
Tag: \(20 - 10 - 4 = 6\) bits.

Each of the \(2^{10}\) cache lines stores its own 6-bit tag, so the tag storage is \(6 \times 2^{10}\) bits.

Answer: A

GATE CS 2025 Set 1 | Question 37

MCQ · 2 marks · −0.66

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25     // R1 = R1 + 25

16 20 22 24

Explanation

Answer: (B)

The 32-bit instruction must hold the opcode, one register field (R1) and the immediate value; the immediate gets whatever bits are left.

Opcode: 50 instruction types need 6 bits, since \(2^5 = 32 \lt 50 \le 64 = 2^6\).
Register: 64 registers need \(\log_2 64 = 6\) bits.
Immediate: \(32 - 6 - 6 = 20\) bits.

Answer: B

GATE CS 2025 Set 1 | Question 53

NAT · 2 marks

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ________. (rounded off to two decimal places)

Processor, then L1 cache (hit rate 95%, access time 10 ns), then L2 cache (hit rate 85%, access time including L1 cache miss penalty 20 ns), then main memory (access time including L1 and L2 cache miss penalty 200 ns)

Your answer

Explanation

Answer: 11.83 to 11.87

The L2 and main-memory times already include the time lost on the earlier misses, so each path is simply weighted by its probability.

L1 hit: probability \(0.95\), time 10 ns.
L1 miss, L2 hit: probability \(0.05 \times 0.85 = 0.0425\), time 20 ns.
Both miss: probability \(0.05 \times 0.15 = 0.0075\), time 200 ns.

\[T_{\text{avg}} = 0.95(10) + 0.0425(20) + 0.0075(200) = 9.5 + 0.85 + 1.5 = 11.85 \text{ ns}\]

Answer: 11.85

GATE CS 2025 Set 2 | Question 28

MSQ · 1 mark

Which of the following is/are part of an Instruction Set Architecture of a processor?

The size of the cache memory The clock frequency of the processor The number of cache memory levels The total number of registers

Explanation

Answer: (D)

The ISA is the contract between hardware and software: what a compiler or assembly programmer must know to write correct machine code. It covers the instructions and their encodings, the addressing modes, the data types and the programmer-visible registers. Instructions name registers by number, so the number of registers is fixed by the ISA (D).

Cache size, the number of cache levels and the clock frequency are implementation (microarchitecture) choices. Processors with the same ISA differ in all three yet run the same programs unchanged, only at different speeds. So (A), (B) and (C) are not part of the ISA.

Answer: D

GATE CS 2025 Set 2 | Question 32

NAT · 1 mark

The following two signed 2’s complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth’s algorithm:

M: 1100 1101 1110 1101 and Q: 1010 0100 1010 1010

The total number of addition and subtraction operations to be performed is ___________. (Answer in integer)

Your answer

Explanation

Answer: 13

Booth's algorithm looks at each multiplier bit \(Q_i\) together with the bit to its right, \(Q_{i-1}\), taking \(Q_{-1} = 0\). The pair 10 subtracts M, the pair 01 adds M, and 00 or 11 only shifts. So the number of operations is the number of adjacent bit pairs that differ once a 0 is appended to Q; the multiplicand M plays no part.

Q with the extra bit is 1010 0100 1010 1010 0. Of its 16 adjacent pairs, only 3 are equal (the three 00 pairs). The other 13 each cost one operation: 7 subtractions (pair 10) and 6 additions (pair 01).

Answer: 13

GATE CS 2025 Set 2 | Question 39

MCQ · 2 marks · −0.66

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.

Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?

64 KB and 4 KB 128 KB and 16 KB 64 KB and 8 KB 128 KB and 6 KB

Explanation

Answer: (A)

Each block holds one byte, so the address has no offset field: it is just tag plus index, \(4 + 12 = 16\) bits.

Main memory: \(2^{16}\) bytes = 64 KB.
Cache: the index picks one of \(2^{12}\) blocks of 1 byte each, so the cache holds \(2^{12}\) bytes = 4 KB.

Option D’s 6 KB would add the 4-bit tags to the data (12 bits per block), and its 128 KB would need a 17-bit address, so it does not fit.

Answer: A

GATE CS 2025 Set 2 | Question 55

NAT · 2 marks

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is ___________ . (rounded off to one decimal place)

Your answer

Explanation

Answer: 4

Every access pays the L1 time of 1 ns. The 10% of accesses that miss in L1 pay 10 ns to fetch from L2, and the 20% of those that also miss in L2 pay a further 100 ns to bring the data from main memory:

\[\text{AMAT} = 1 + 0.1 \times (10 + 0.2 \times 100) = 1 + 0.1 \times 30 = 4.0\ \text{ns}\]

A common slip is to charge the 100 ns to 20% of all accesses (giving 22 ns). It applies only to the \(0.1 \times 0.2 = 2\%\) of accesses that miss in both caches.

Answer: 4.0

GATE CS 2025 Set 2 | Question 56

NAT · 2 marks

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)

Your answer

Explanation

Answer: 260.2 to 261.2

The clock must fit the slowest stage plus a latch: \(T = 250 + 10 = 260\) ns.

With no stalls, the first instruction takes 5 cycles to pass through the pipeline and each of the other 999 instructions finishes one cycle after the previous one:

\[(5 + 1000 - 1) \times 260 = 1004 \times 260 = 261040\ \text{ns} = 261.04\ \mu\text{s}\]

Using the average stage delay, or leaving out the latch delay, gives a clock that is too short: every stage advances in lockstep, so the slowest stage sets the pace.

Answer: 261.04

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