Computer Organization and Architecture

The total number of clock cycles is the CPI-weighted sum of the instruction counts:

\[(2 \times 2.25 + 5 \times 1.20 + 4 \times 1.65 + 3 \times 1.30) \times 10^{8} = (4.5 + 6.0 + 6.6 + 3.9) \times 10^{8} = 21 \times 10^{8}\]

The four counts add up to \(6.4 \times 10^{8}\), as stated, so the average CPI is \(21 / 6.4 \approx 3.28\).

Dividing the run time by the cycle count gives the clock cycle time:

\[\frac{6.3\ \text{s}}{21 \times 10^{8}} = 3 \times 10^{-9}\ \text{s} = 3.0\ \text{ns}\]

Answer: 3.0

Statement C is false. In programmed I/O the CPU keeps polling the device status until it is ready, so its cycles are wasted in busy-waiting. Interrupt-driven I/O lets the CPU do other work and respond only when the device raises an interrupt, so it gives better CPU utilization, not worse.

The other statements are true:

• A: in cycle stealing, the DMA controller takes the bus for one cycle and moves one word.
• B: burst mode keeps the bus for the whole block, so bulk transfers finish sooner.
• D: a vectored interrupt supplies the address of its service routine, so the CPU need not poll devices to find the source.

Answer: C

• A: true. This is what forwarding (bypassing) means: a result goes straight from the stage that produces it in an earlier instruction to the stage that needs it in a later one, without waiting for the register write in WB.
• B: true. The MEM/WB pipeline register holds what leaves the MEM stage, such as a loaded word, and a forwarding path takes it to the ALU inputs in EX. A loaded value reaches the very next instruction this way after one stall cycle.
• C: true. That stall is unavoidable: a loaded value appears only at the end of MEM, while the next instruction needs it at the start of EX in the same cycle.
• D: false. Forwarding needs extra paths, multiplexers at the ALU inputs and a forwarding unit that compares register numbers.

Answer: A, B, C

• (A) False: on a read miss in a full set, LRU picks the victim without looking at its dirty bit. In a write back cache that block may be dirty, and it is then written back before the new block is brought in.
• (B) True: write through updates main memory on every write, so no cache block is ever newer than memory and evicting one needs no write back.
• (C) True: a write hit in a write back cache updates only the cache and sets the dirty bit, which changes it from 0 to 1 if the block was clean.
• (D) False: in a write through cache the victim already matches main memory, so it is simply overwritten. Nothing is written back first (and with no-write-allocate the missed block is not loaded at all).

Answer: B, C

A cylinder is the set of tracks at one arm position, one track on each of the 32 surfaces.

• Bytes per track: \(4096 \times 1024 = 2^{12} \times 2^{10} = 2^{22}\) bytes (4 MB).
• Bytes per cylinder: \(32 \times 2^{22} = 2^{5} \times 2^{22} = 2^{27}\) bytes (128 MB).
• Number of cylinders: \(2^{39} / 2^{27} = 2^{12} = 4096\), since \(512\ \text{GB} = 2^{9} \times 2^{30} = 2^{39}\) bytes.

The number of cylinders is the same as the number of tracks on one surface.

Answer: 4096

Of the 100 ns, 10 ns is serial and 90 ns can be shared. With \(p\) cores the shared part takes \(90/p\) ns, and each of the \(p - 1\) additional cores costs 10 ns:

\[T(p) = 10 + \frac{90}{p} + 10(p - 1)\]

This gives \(T(1) = 100\), \(T(2) = 65\), \(T(3) = 60\), \(T(4) = 62.5\) and \(T(5) = 68\) ns. A fourth core saves only \(30 - 22.5 = 7.5\) ns on the parallel part but adds 10 ns of overhead, so the time is smallest with 3 cores.

Charging the overhead for every core (\(10p\)) raises each time by 10 ns and still gives 3. The 2 GHz clock rate plays no part.

Answer: 3

Every instruction is fetched, so each one accesses the instruction cache once, while only the 25% load/store instructions also access the data cache. Memory stall cycles per instruction:

\[1 \times 0.02 \times 100 + 0.25 \times 0.08 \times 100 = 2 + 2 = 4\]

The real CPI is therefore \(2 + 4 = 6\), while a perfect cache gives the ideal CPI of 2. The instruction count and clock are the same in both cases, so the speedup is \(6 / 2 = 3.00\).

Applying the 8% data miss rate to every instruction gives a CPI of 12 and a speedup of 6, which overcounts the data accesses.

Answer: 3.00

A 4 MHz processor runs \(4 \times 10^{6}\) cycles per second. With cycle stealing, the DMA controller gets 1% of them:

\[0.01 \times 4 \times 10^{6} = 4 \times 10^{4} \text{ cycles per second}.\]

Each stolen cycle moves 8 bytes, that is \(8 \times 8 = 64\) bits, so the transfer rate is

\[4 \times 10^{4} \times 64 = 2.56 \times 10^{6} \text{ bits per second},\]

which is written 25,60,000 in the Indian digit grouping used by the options. Note that the rate is asked in bits, so the 8 bytes per cycle must be multiplied by 8.

Answer: C

Take an earlier instruction and a later one. RAW (read after write) means the later one reads a register that the earlier one writes, WAR means the later one writes a register that the earlier one reads, and WAW means both write the same register. Here R3 is written by I1 and I3 and read by I2 and I4.

• A: I1 writes R3 and I2 reads it. RAW, so true.
• B: I1 and I3 both write R3, and I1 does not read it. That is WAW, not WAR.
• C: I2 reads R3 and the later I3 writes it. That is WAR, not RAW (the RAW between them is on R5).
• D: I3 writes R3 and I4 reads it. That is RAW, not WAW; I4 writes R7.

Answer: A

Add up the fixed fields of the 32-bit instruction:

• each register field names one of 16 registers, so it needs \(\log_2 16 = 4\) bits, and the two fields take 8 bits;
• 8 addressing modes need \(\log_2 8 = 3\) bits;
• the scalar field takes 16 bits.

That leaves \(32 - 8 - 3 - 16 = 5\) bits for the opcode, so at most \(2^{5} = 32\) opcodes can be encoded. The mode has its own field, so all 32 opcodes can be combined with each of the 8 addressing modes.

Answer: 32