Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
Answer
(C)
Explanation
A 4 MHz processor runs \(4 \times 10^{6}\) cycles per second. With cycle stealing, the DMA controller gets 1% of them:
\[0.01 \times 4 \times 10^{6} = 4 \times 10^{4} \text{ cycles per second}.\]
Each stolen cycle moves 8 bytes, that is \(8 \times 8 = 64\) bits, so the transfer rate is
\[4 \times 10^{4} \times 64 = 2.56 \times 10^{6} \text{ bits per second},\]
which is written 25,60,000 in the Indian digit grouping used by the options. Note that the rate is asked in bits, so the 8 bytes per cycle must be multiplied by 8.
Answer: C