GATE CS Interrupts and I/O Previous Year Questions

GATE CS 2025 Set 1 | Question 11

MCQ · 1 mark · −0.33

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

(iii), (i), (ii) (i), (iii), (ii) (i), (ii), (iii) (iii), (ii), (i)

Explanation

Answer: (A)

A non-pipelined processor checks for interrupts only between instructions, so it first completes the instruction it is executing (iii). Next it saves the program counter (i), which now holds the address of the next instruction, so the interrupted program can continue from there once the ISR returns. Only then is the program counter loaded with the ISR's start address (ii); doing (ii) before (i) would destroy the return address.

Answer: A

GATE CS 2024 Set 1 | Question 15

MCQ · 1 mark · −0.33

Which one of the following statements is FALSE?

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Explanation

Answer: (C)

Statement C is false. In programmed I/O the CPU keeps polling the device status until it is ready, so its cycles are wasted in busy-waiting. Interrupt-driven I/O lets the CPU do other work and respond only when the device raises an interrupt, so it gives better CPU utilization, not worse.

The other statements are true:

A: in cycle stealing, the DMA controller takes the bus for one cycle and moves one word.
B: burst mode keeps the bus for the whole block, so bulk transfers finish sooner.
D: a vectored interrupt supplies the address of its service routine, so the CPU need not poll devices to find the source.

Answer: C

GATE CS 2024 Set 2 | Question 11

MCQ · 1 mark · −0.33

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

2,56,000 3,200 25,60,000 32,000

Explanation

Answer: (C)

A 4 MHz processor runs \(4 \times 10^{6}\) cycles per second. With cycle stealing, the DMA controller gets 1% of them:

\[0.01 \times 4 \times 10^{6} = 4 \times 10^{4} \text{ cycles per second}.\]

Each stolen cycle moves 8 bytes, that is \(8 \times 8 = 64\) bits, so the transfer rate is

\[4 \times 10^{4} \times 64 = 2.56 \times 10^{6} \text{ bits per second},\]

which is written 25,60,000 in the Indian digit grouping used by the options. Note that the rate is asked in bits, so the 8 bytes per cycle must be multiplied by 8.

Answer: C