Computer Organization and Architecture

GATE CS previous year questions · 22 questions

GATE CS 2024 Set 2 | Question 58

NAT · 2 marks

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

Explanation

Answer: 2.9 to 3.1

Both designs run at the same 2 GHz clock, so the speedup is the ratio of their cycles per instruction (CPI).

  • Non-pipelined CPI: 6.
  • Pipelined CPI: the ideal 1 plus the average stall cycles, \(1 + 0.2 \times 2 + 0.2 \times 3 = 1 + 0.4 + 0.6 = 2\).

Speedup \(= 6 / 2 = 3.0\). The number of stages does not enter the calculation, because the pipelined throughput (1 instruction per cycle) and the non-pipelined cycle count (6) are both given directly.

Answer: 3.0

GATE CS 2024 Set 2 | Question 61

NAT · 2 marks

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:
OPCODEUNUSEDDST RegisterSRC Register1SRC Register 2
I-type Instruction Format:
OPCODEDST RegisterSRC Register# Immediate value/address

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let \(X\) be the number of bits used to encode the UNUSED field, \(Y\) be the number of bits used to encode the OPCODE field, and \(Z\) be the number of bits used to encode the immediate value/address field. The value of \(X + 2Y + Z\) is ________

Explanation

Answer: 34

Find each field width:

  • Registers: 50 registers need \(\lceil \log_2 50 \rceil = 6\) bits per register field.
  • OPCODE: each type has \(150 / 2 = 75\) operations, which need 7 bits (\(2^{7} = 128\)); with the type bit, \(Y = 8\).
  • R-type: \(8 + X + 3 \times 6 = 32\), so \(X = 6\).
  • I-type: \(8 + 2 \times 6 + Z = 32\), so \(Z = 12\).

Hence \(X + 2Y + Z = 6 + 16 + 12 = 34\). The result does not depend on how the opcode is sized: \(X = 14 - Y\) and \(Z = 20 - Y\), so the sum is 34 either way.

Answer: 34