A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.
| OPCODE | UNUSED | DST Register | SRC Register1 | SRC Register 2 |
| OPCODE | DST Register | SRC Register | # Immediate value/address |
In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.
Let \(X\) be the number of bits used to encode the UNUSED field, \(Y\) be the number of bits used to encode the OPCODE field, and \(Z\) be the number of bits used to encode the immediate value/address field. The value of \(X + 2Y + Z\) is ________
Answer
34
Explanation
Find each field width:
- Registers: 50 registers need \(\lceil \log_2 50 \rceil = 6\) bits per register field.
- OPCODE: each type has \(150 / 2 = 75\) operations, which need 7 bits (\(2^{7} = 128\)); with the type bit, \(Y = 8\).
- R-type: \(8 + X + 3 \times 6 = 32\), so \(X = 6\).
- I-type: \(8 + 2 \times 6 + Z = 32\), so \(Z = 12\).
Hence \(X + 2Y + Z = 6 + 16 + 12 = 34\). The result does not depend on how the opcode is sized: \(X = 14 - Y\) and \(Z = 20 - Y\), so the sum is 34 either way.
Answer: 34