GATE CS Machine Instructions and Addressing Modes Previous Year Questions

GATE CS 2025 Set 1 | Question 37

MCQ · 2 marks · −0.66

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25     // R1 = R1 + 25

16 20 22 24

Explanation

Answer: (B)

The 32-bit instruction must hold the opcode, one register field (R1) and the immediate value; the immediate gets whatever bits are left.

Opcode: 50 instruction types need 6 bits, since \(2^5 = 32 \lt 50 \le 64 = 2^6\).
Register: 64 registers need \(\log_2 64 = 6\) bits.
Immediate: \(32 - 6 - 6 = 20\) bits.

Answer: B

GATE CS 2025 Set 2 | Question 28

MSQ · 1 mark

Which of the following is/are part of an Instruction Set Architecture of a processor?

The size of the cache memory The clock frequency of the processor The number of cache memory levels The total number of registers

Explanation

Answer: (D)

The ISA is the contract between hardware and software: what a compiler or assembly programmer must know to write correct machine code. It covers the instructions and their encodings, the addressing modes, the data types and the programmer-visible registers. Instructions name registers by number, so the number of registers is fixed by the ISA (D).

Cache size, the number of cache levels and the clock frequency are implementation (microarchitecture) choices. Processors with the same ISA differ in all three yet run the same programs unchanged, only at different speeds. So (A), (B) and (C) are not part of the ISA.

Answer: D

GATE CS 2024 Set 2 | Question 57

NAT · 2 marks

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is _________

Your answer

Explanation

Answer: 32

Add up the fixed fields of the 32-bit instruction:

each register field names one of 16 registers, so it needs \(\log_2 16 = 4\) bits, and the two fields take 8 bits;
8 addressing modes need \(\log_2 8 = 3\) bits;
the scalar field takes 16 bits.

That leaves \(32 - 8 - 3 - 16 = 5\) bits for the opcode, so at most \(2^{5} = 32\) opcodes can be encoded. The mode has its own field, so all 32 opcodes can be combined with each of the 8 addressing modes.

Answer: 32

GATE CS 2024 Set 2 | Question 61

NAT · 2 marks

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:
OPCODE	UNUSED	DST Register	SRC Register1	SRC Register 2

I-type Instruction Format:
OPCODE	DST Register	SRC Register	# Immediate value/address

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let \(X\) be the number of bits used to encode the UNUSED field, \(Y\) be the number of bits used to encode the OPCODE field, and \(Z\) be the number of bits used to encode the immediate value/address field. The value of \(X + 2Y + Z\) is ________

Your answer

Explanation

Answer: 34

Find each field width:

Registers: 50 registers need \(\lceil \log_2 50 \rceil = 6\) bits per register field.
OPCODE: each type has \(150 / 2 = 75\) operations, which need 7 bits (\(2^{7} = 128\)); with the type bit, \(Y = 8\).
R-type: \(8 + X + 3 \times 6 = 32\), so \(X = 6\).
I-type: \(8 + 2 \times 6 + Z = 32\), so \(Z = 12\).

Hence \(X + 2Y + Z = 6 + 16 + 12 = 34\). The result does not depend on how the opcode is sized: \(X = 14 - Y\) and \(Z = 20 - Y\), so the sum is 34 either way.

Answer: 34