A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________
Answer
2.9 to 3.1
Explanation
Both designs run at the same 2 GHz clock, so the speedup is the ratio of their cycles per instruction (CPI).
- Non-pipelined CPI: 6.
- Pipelined CPI: the ideal 1 plus the average stall cycles, \(1 + 0.2 \times 2 + 0.2 \times 3 = 1 + 0.4 + 0.6 = 2\).
Speedup \(= 6 / 2 = 3.0\). The number of stages does not enter the calculation, because the pipelined throughput (1 instruction per cycle) and the non-pipelined cycle count (6) are both given directly.
Answer: 3.0