GATE CS 2019 — Question 11
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and…
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GATE CS — Computer Science & IT
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GATE CS 2018 — Question 33
The size of the physical address space of a processor is \(2^{P}\) bytes. The word length is \(2^{W}\) bytes. The capacity of cache memory is \(2^{N}\) bytes. The…
GATE CS 2016 Set 1 — Question 22
A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of…
GATE CS 2017 Set 1 — Question 45
Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1…
GATE CS 2015 Set 3 — Question 40
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the…
GATE CS 2015 Set 1 — Question 34
Consider a machine with a byte addressable main memory of \(2^{20}\) bytes, block size of 16 bytes and a direct mapped cache having \(2^{12}\) cache lines. Let the…
GATE CS 2014 Set 2 — Question 43
Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage…
GATE CS 2008 — Question 33
Which of the following are true of the auto-increment addressing mode?I. It is useful in creating self-relocating code.II. If it is included in an Instruction Set Architecture, then…
GATE CS 2012 — Question 10
The decimal value 0.5 in IEEE single precision floating point representation has
GATE CS 2006 — Question 41
A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the…
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