GATE CS 2017 Set 1 — Question 45

Numerical answer 2 marks Question 45 2017

Question 45

NAT 2 marks · no negative Computer Organization and Architecture

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______.

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GATE CS — Computer Science & IT 2017 Computer Organization and Architecture

Source: GATE 2017 Computer Science and Information Technology, Set 1 (question number approximate)

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