Computer Organization and Architecture — GATE Previous Year Questions

Consider a small two-way set associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is

8, 12, 0, 12, 8

A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes \(10^{9}\) instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is

Which of the following are true of the auto-increment addressing mode?

I. It is useful in creating self-relocating code.
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation.
III. The amount of increment depends on the size of the data item accessed.

The decimal value 0.5 in IEEE single precision floating point representation has

Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ______.

Consider a machine with a byte addressable main memory of \(2^{20}\) bytes, block size of 16 bytes and a direct mapped cache having \(2^{12}\) cache lines. Let the addresses of two consecutive bytes in main memory be \((\text{E}201\text{F})_{16}\) and \((\text{E}2020)_{16}\). What are the tag and cache line address (in hex) for main memory address \((\text{E}201\text{F})_{16}\)?

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location \((0100)_{16}\) and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is \((016\text{E})_{16}\). The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack
• Store the value of PSW register in the stack
• Load the starting address of the subroutine in PC

The content of PC just before the fetch of a CALL instruction is \((5\text{F}\text{A}0)_{16}\). After execution of the CALL instruction, the value of the stack pointer is

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ______ bits.

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______.

The size of the physical address space of a processor is \(2^{P}\) bytes. The word length is \(2^{W}\) bytes. The capacity of cache memory is \(2^{N}\) bytes. The size of each cache block is \(2^{M}\) words. For a \(K\)-way set-associative cache memory, the length (in number of bits) of the tag field is

A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for Tag and Index fields respectively in the addresses generated by the processor?

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is ______.