GATE CS 2024 Set 1 | Question 28
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

Explanation
Answer: (A), (C)
The AND gate receives \(X\) directly and \(\overline{X}\) through the inverter, so ideally \(Y = X \cdot \overline{X} = 0\) for every input: A is true and B is false.
Now let the NOT gate take time \(t\) to respond.
- \(X\) rises from 0 to 1: the direct input becomes 1 at once, but for time \(t\) the inverter still outputs its old value 1. Both AND inputs are briefly 1, so \(Y\) shows a short glitch to logic One (a static hazard). C is true.
- \(X\) falls from 1 to 0: the direct input drops to 0 at once, while the inverter output is still 0 and rises only after \(t\). The two inputs are never 1 together, so \(Y\) simply stays at 0. With no 1 to dip from, no transient Zero can appear, so D is false.
Answer: A, C

